ヤナセ　タカシ   Yanase Takashi   柳瀨　隆    所属   東邦大学  理学部 化学科    職種   講師
論文種別	原著
言語種別	英語
査読の有無	査読あり
表題	Electric Double Layer Gate Field-Effect Transistors Based on Si
掲載誌名	正式名：JAPANESE JOURNAL OF APPLIED PHYSICS ISSNコード：0021-4922
出版社	JAPAN SOC APPLIED PHYSICS
巻・号・頁	49(4)
著者・共著者	Takashi Yanase,Toshihiro Shimada,Tetsuya Hasegawa
発行年月	2010/04/20
概要	Electric double layer field-effect transistors (EDL-FETs) were fabricated using single crystal Si wafer as the active semiconductor and various characteristics were studied including dynamic response against step-function gate bias. The static FET mobility was more than 100 cm(2) V-1 s(-1). The response time of the drain current was 20 mu s for ionic liquid and 3 ms for poly(ethylene glycol) (PEG) solution of LiBF4. Unexpected fast response was observed at a certain "speed up bias'' condition. This effect will be useful to switching circuits using EDL-FETs. (C) 2010 The Japan Society of Applied Physics
DOI	10.1143/JJAP.49.04DK06
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